Capacitors are widely used in integrated circuits. FIG. 1 is a block diagram illustrating a cross section of an integrated circuit (IC) device 100 including an interconnect stack 110. The interconnect stack 110 of the IC device 100 includes multiple conductive interconnect layers (M1, . . . , M9, M10) on a semiconductor substrate (e.g., a silicon wafer) 102. The semiconductor substrate 102 supports metal oxide metal (MOM) capacitors 130. In this example, a first MOM capacitor 130A is formed in the M3 and M4 interconnect layers, and a second MOM capacitor 130B is formed in the M5 and M6 interconnect layers. The MOM capacitors 130 (130A and 130B) are formed from lateral conductive fingers of different polarities using the conductive interconnect layers (M3 and M4/M5 and M6) of the interconnect stack 110. An dielectric (not shown) is provided between the conductive fingers.
In this example, the MOM capacitors 130 are formed within the lower conductive interconnect layers (e.g., M1-M6) of the interconnect stack 110. The lower conductive interconnect layers of the interconnect stack 110 have smaller interconnect widths and spaces. For example, the dimensions of the conductive interconnect layers M3 and M4 are half the size of the dimensions of the conductive interconnect layers M5 and M6. Likewise, the dimensions of the conductive interconnect layers M1 and M2 are half the size of the dimensions of the conductive interconnect layers M3 and M4. The small interconnect widths and spaces of the lower conductive interconnect layers enable the formation of MOM capacitors with increased capacitance density.
As shown in FIG. 1, the MOM capacitors 130 make use of a lateral (intra layer) capacitive coupling 140 between fingers formed by standard metallization of the conductive interconnects (e.g., wiring lines and vias). The lateral coupling 140 within the MOM capacitors 130 provides improved matching characteristics when compared to the vertical coupling of parallel vertical plate capacitors. The improved matching characteristics of the MOM capacitors 130 are the result of improved process control of the lateral dimensions within the interconnect stack 110. By contrast, the process controls of the vertical dimensions of the conductive interconnect and dielectric layer thickness within the interconnect stack 110 are less precise for providing small value capacitance.
It is becoming significantly more challenging to fabricate high density capacitance. Consequently, using only MOM capacitors in future process technologies may be insufficient to provide high density capacitance for IC devices.
A metal insulator metal (MIM) capacitor in the back end of line (BEOL) layers has been proposed. The MIM capacitor uses vertical plate to plate coupling. This solution, however, involves additional masks as well as a high-K (HiK) oxide deposition process to achieve an increased capacitor density. In addition, MIM capacitors are generally formed between the upper conductive interconnect layers (e.g., M9 and M10) of the interconnect stack 110.